Design and implementation of payload data handling based on field programmable gate array

In order to transmit large amount of various payload data with the limited capacity channel, satellite requires payload data handling system. This paper presents the design and implementation of payload data handling for microsatellite based on FPGA Altera Cyclone IV EP4CE115F29C7. The proposed payload data handling design was divided into two main modules, CCSDS packet module and Reed-Solomon encoder module. Both modules were based on Packet Telemetry CCSDS recommendation. We proposed to use Reed-Solomon (223,255,16) interleave 5 for the outer code. Then followed by pseudo-random sequence and attached sync marker. The functional and performance test result shows and verify the functionality of Payload data handling FPGA implementation. The time required for generating 1 Frame was 54.68 ms for 25 Mbps. In order to synchronize the frame delay transition it requires 89 bytes dummy data. The proposed design uses 1627 total logic element and 92160 bit memory.