A 2.5 GHz low phase noise oscillator design in 65nm CMOS technology with reduced current consumption

Author

Dossou, Siegfried ; Joblot, S. ; Petit, D. ; Ancey, P.

Author_Institution

STMicroelectron., Crolles

fYear

2008

fDate

8-10 Dec. 2008

Firstpage

1

Lastpage

4

Abstract

A 2.5 GHz low phase noise oscillator is presented in this paper. The oscillator was design using a Solidly Mounted BAW Resonator (SMR BAW) as resonant element. The resonator exhibits a parallel resonance Q factor around 1300 at 2.54 GHz. The core oscillator was designed using STMicroelectronics 65 nm CMOS technology. It exhibits 632 mV output (zero-to-pic) with phase noise performance of -92 dBc/Hz, -109 dBc/Hz, and -130 dBc/Hz at 2 KHz, 10 KHz and 100 KHz respectively. It consumes 1 mA from a 1.2 V source.

Keywords

CMOS integrated circuits; Q-factor; UHF integrated circuits; UHF oscillators; acoustic resonators; bulk acoustic wave devices; integrated circuit noise; phase noise; CMOS technology; frequency 2.5 GHz; low phase noise oscillator design; parallel resonance Q factor; reduced current consumption; size 65 nm; solidly mounted BAW resonator; 1f noise; CMOS technology; Circuit noise; Frequency; Low-frequency noise; Oscillators; Phase noise; Q factor; Resonance; Tail;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices and Solid-State Circuits, 2008. EDSSC 2008. IEEE International Conference on

Conference_Location

Hong Kong

Print_ISBN

978-1-4244-2539-6

Electronic_ISBN

978-1-4244-2540-2

Type

conf

DOI

10.1109/EDSSC.2008.4760724

Filename

4760724