FPGA Implementation of Evolvable Block-based Neural Networks

This paper presents a hardware implementation approach for block-based neural networks (BbNNs) on a Programmable System-On-Chip. This is an intrinsic online evolution system that can be genetically evolved and adapted to changes in input data patterns dynamically without any need for multiple FPGA reconfigurations to accommodate various network structure/parameter changes. This removes a considerable bottleneck for performance. The research presented here is a first step towards an evolvable system that can be implemented as an embedded system.