Graph Theoretical Representation of Grid-based ANN Architectures for VLSI Implementations

The System-on-Chip design of purely digital architectures, which are based on massively parallel Markov random field (MRF) processing principles is so far an unstructured, time consuming, fault-prone and complex task. Up to now a toolkit is not available to systematically support the VLSI design task in a single coherent environment and along a seamless design flow for various digital semiconductor-technologies. In this contribution we report on a completely technology-independent and graph-theoretical approach for the VLSI design of massively parallel MRF processing devices. The paper is finalized by selected results, which show generated graphs, synthesis results and prototypical implementations in FPGA technologies. All together these results demonstrate the ability of the proposed graph-theoretical approach and manifest the industrial relevance of the developed tool-kit.