Design and implementation of LDPC(Low Density Parity Check) coding technique on FPGA (Field Programmable Gate Array) for DVB-S2 (Digital Video Broadcasting-Satellite)

Author

Purnamasari, Rita ; Wijanto, Heroe ; Hidayat, Iswahyudi

Author_Institution

Electr. Eng. Fac., Telkom Univ., Bandung, Indonesia

fYear

2014

fDate

13-14 Nov. 2014

Firstpage

83

Lastpage

88

Abstract

LDPC (Low Density Parity Check) is a channel coding technique is used to correct errors so that the validity of a data transmission on the noise transmission channel guaranteed for accuracy. LDPC is suitable for applications that require a large bandwidth, high reliability, and high noise channel like DVB-S2 (Digital Video Broadcast-Satellite) application. Despite the high level of complexity, LDPC coding technique is very possible to be implemented in line with the growing hardware capabilities. The purpose of this research later is to make DVB-S2 chips that can transmit digital video via satellite.

Keywords

channel coding; data communication; digital video broadcasting; error correction; field programmable gate arrays; logic design; parity check codes; DVB-S2 chips; FPGA; LDPC channel coding technique design; complexity level; data transmission; digital video broadcasting-satellite; error correction; field programmable gate array; hardware capability; high noise channel; high reliability channel; large bandwidth channel; low density parity check coding technique; noise transmission channel; Clocks; Decoding; Digital video broadcasting; Encoding; Field programmable gate arrays; Mathematical model; Parity check codes; DVB-S (Digital); FPGA(Field Programmable Gate Array) Virtex-4; LDPC(Low Density Parity Check); bit flipping; lower triangular;

fLanguage

English

Publisher

ieee

Conference_Titel

Aerospace Electronics and Remote Sensing Technology (ICARES), 2014 IEEE International Conference on

Conference_Location

Yogyakarta

Print_ISBN

978-1-4799-6187-0

Type

conf

DOI

10.1109/ICARES.2014.7024407

Filename

7024407