Title :
2006 Design Automation Conference (IEEE Cat. No. 06CH37797)
Abstract :
The following topics are dealt with: hierarchical synthesis for mixed-signal designs; processor and communication centric SOC design; design for manufacturability; RTL verification; MPSOC design methodologies; statistical timing analysis; power grid analysis; gate modelling; model order reduction; buffer insertion; timing defects; routing; variation-aware analysis; FPGA; logic synthesis; thermal-aware architectures; low power system level design; power-constrained design for multimedia; communication-driven synthesis; memory optimizations; nanotubes and nanowires; formal verification; yield analysis; soft error mitigation; network-on-chip; analog design; dataflow models; biochip design; low power circuit design; interconnect extraction; and automatic test pattern generation.
Keywords :
automatic test pattern generation; design for manufacture; field programmable gate arrays; formal verification; hardware description languages; integrated circuit design; integrated circuit interconnections; integrated circuit yield; microprocessor chips; nanotubes; nanowires; system-on-chip; FPGA; RTL verification; analog design; automatic test pattern generation; biochip design; buffer insertion; communication-driven synthesis; dataflow models; design for manufacturability; formal verification; gate modeling; interconnect extraction; logic synthesis; memory optimizations; mixed-signal designs; model order reduction; nanotubes; nanowires; network routing; network-on-chip; power grid analysis; processor design; statistical timing analysis; system-on-chip design; thermal-aware architectures; timing defects; yield analysis;
Conference_Titel :
Design Automation Conference, 2006 43rd ACM/IEEE
Conference_Location :
San Francisco, CA
Print_ISBN :
1-59593-381-6
DOI :
10.1109/DAC.2006.238664
