An automated, reconfigurable, low-power RFID tag

Author

Jones, Alex K. ; Hoare, Raymond R. ; Dontharaju, Swapna R. ; Tung, Shenchih ; Sprang, Ralph ; Fazekas, Josh ; Cain, XJames T. ; Mickle, Marlin H.

Author_Institution

Dept. of Electr. & Comput. Eng., Pittsburgh Univ., PA

fYear

0

fDate

0-0 0

Firstpage

131

Lastpage

136

Abstract

This paper describes an ultra low power active RFID tag and its automated design flow. RFID primitives to be supported by the tag are enumerated with RFID macros and the behavior of each primitive is specified using ANSI-C within the template to automatically generate the tag controller. Two power saving components, a passive transceiver/burst switch and a smart buffer, are presented to save power and increase tag lifetime. Based on a test program, the processors required 183, 43, and 19 muJ per transaction for StrongARM, XScale, and EISC processors, respectively. Three hardware controllers using a Fusion FPGA, Coolrunner II CPLD, and ASIC required 13 nJ, 1.3 nJ, and 0.07 nJ per transaction

Keywords

buffer circuits; integrated circuit design; logic design; low-power electronics; microprocessor chips; radiofrequency identification; transceivers; ANSI-C; ASIC; Coolrunner II CPLD; EISC processors; Fusion FPGA; StrongARM processors; XScale processors; active RFID tag; automated design flow; burst switch; passive transceiver; reconfigurable RFID tag; smart buffer; tag controller; Active RFID tags; Automatic generation control; Field programmable gate arrays; Hardware; RFID tags; Radiofrequency identification; Switches; Temperature control; Testing; Transceivers; Design; Human Factors; Languages; Performance;

fLanguage

English

Publisher

ieee

Conference_Titel

Design Automation Conference, 2006 43rd ACM/IEEE

Conference_Location

San Francisco, CA

ISSN

0738-100X

Print_ISBN

1-59593-381-6

Type

conf

DOI

10.1109/DAC.2006.229191

Filename

1688776