Power architecture design with improved system efficiency, EMI and power density

The optimized design of power architecture is discussed in this paper. The paper first discusses the asymmetrical interleaved multi-channel PFC technique and its benefits to system power density and the reduction of differential mode noise. A balance technique is then proposed to minimize the common mode noise of asymmetrical interleaved multi-channel PFC. Greatly reduced EMI leads to the size reduction of EMI filters. System power density is therefore improved. For DC/DC stage, a 1 MHz, LLC resonant converter with novel synchronous rectifier is proposed to reduce body diode conduction time. Both conduction loss and reverse recovery loss can be reduced. The whole system´s efficiency, EMI and power density can be greatly improved by applying the techniques proposed in this paper.