Reliability challenges for 45nm and beyond

Author

McPherson, J.W.

Author_Institution

Texas Instruments, Inc., Dallas, TX

fYear

0

fDate

0-0 0

Firstpage

176

Lastpage

181

Abstract

Scaling, for enhanced performance and cost reduction, has pushed existing CMOS materials much closer to their intrinsic reliability limits. This requires that designers have to be very careful with: high current densities, voltage overshoots, and localized hot spots on the chip, high duty-cycle applications, and high thermal-resistance packaging. In addition to the reliability issues, interconnect RC time-delay worsen with scaling because Cu resistivity is expected to increase due to surface and grain boundary scattering in very narrow interconnects. Also, the low-k interconnect-dielectric introduction rate has been much slower than ITRS roadmap forecasts

Keywords

CMOS integrated circuits; copper; current density; integrated circuit interconnections; integrated circuit reliability; low-k dielectric thin films; nanotechnology; CMOS materials; RC time-delay; current density; grain boundary scattering; high duty-cycle applications; high thermal-resistance packaging; interconnect time delay; intrinsic reliability limits; localized hot spots; low-k dielectric; surface scattering; very narrow interconnects; voltage overshoots; Boundary conditions; CMOS technology; Costs; Dielectrics; Instruments; MOSFET circuits; Materials reliability; Silicides; Thermal resistance; Voltage; CMOS; Design; Performance; Reliability; design; materials; reliability; scaling;

fLanguage

English

Publisher

ieee

Conference_Titel

Design Automation Conference, 2006 43rd ACM/IEEE

Conference_Location

San Francisco, CA

ISSN

0738-100X

Print_ISBN

1-59593-381-6

Type

conf

DOI

10.1109/DAC.2006.229181

Filename

1688785