Modeling and analysis of lateral MOS integrated within power VDMOS for functional integration purposes

The paper deals with the monolithic and functional integration of a gate drivers within a 600 V power VDMOS. The gate driver is based on the N-MOS technique, simple to integrate at reduced technological expense. The analysis is carried out in order to identify the optimal tradeoffs among the lateral and vertical devices in terms of operating characteristics but also performances. Especially, the paper presents how the physical structure and electrical characteristics of the power device can be adjusted in order to emulate a fully isolated and functional lateral N-MOS used afterwards as the main element of the integrated gate driver. The paper addresses static an dynamic issues of the power switch and its integrated gate driver. Susceptibility issues between the power device and the drive parts are not considered in this communication. The analysis is validated by practical results on N-MOS characteristics. Based on the results, estimated gate driver operation is given. It appears that the time domain characteristics can match state of the art discrete CMOS solutions at limited technological expense. This integration effort ends up comparable to CMOS solutions in terms of performances but it adds several advantages such as simplified implementation and reduced electromagnetic coupling interferences.