Title :
Shielding against design flaws with field repairable control logic
Author :
Wagner, Ilya ; Bertacco, Valeria ; Austin, Todd
Author_Institution :
Adv. Comput. Archit. Lab., Michigan Univ., Ann Arbor, MI
Abstract :
Correctness is a paramount attribute of any microprocessor design; however, without novel technologies to tame the increasing complexity of design verification, the amount of bugs that escape into silicon will only grow in the future. In this paper, we propose a novel hardware patching mechanism that can detect design errors which escaped the verification process, and can correct them directly in the field. We accomplish this goal through a simple field-programmable state matcher, which can identify erroneous configurations in the processor\´s control state and switch the processor into formally-verified degraded performance mode, once a "match" occurs. When the instructions exposing the design flaw are committed, the processor is switched back to normal mode. We show that our approach can detect and correct infrequently-occurring errors with almost no performance impact and has approximately 2% area overhead
Keywords :
automatic testing; integrated circuit design; integrated circuit reliability; microprocessor chips; design error detection; design verification; erroneous configuration identification; field repairable control logic; field-programmable state matcher; hardware patching mechanism; microprocessor design; processor verification; Computational modeling; Computer architecture; Computer bugs; Degradation; Error correction; Formal verification; Hardware; Logic design; Pipelines; Switches; Hardware patching; Processor verification; Reliability; Verification;
Conference_Titel :
Design Automation Conference, 2006 43rd ACM/IEEE
Conference_Location :
San Francisco, CA
Print_ISBN :
1-59593-381-6
DOI :
10.1109/DAC.2006.229283