Low jitter ADPLL insensitive to power supply noise

Author

Deng, Xiaoying ; Yang, Jun ; Wu, Jianhui

Author_Institution

China Nat. ASIC Center, Southeast Univ., Nanjing, China

fYear

2010

fDate

14-17 March 2010

Firstpage

1050

Lastpage

1054

Abstract

In this paper an analytical method is presented for estimating the timing jitter of ADPLL due to power supply noise. It leads to the conclusion that jitter heavily depends on the power supply noise frequency and the loop gain. Based on the analytical method, a synthesizable ADPLL with good power supply noise rejection is fabricated in SMIC 0.13μm standard CMOS process, covering 100MHz-500MHz frequency range. The measured Pk-Pk and RMS jitter are 66.7ps and 11.6ps with the power supply noise of 120.8mv.

Keywords

CMOS integrated circuits; digital phase locked loops; interference suppression; noise; power supply quality; timing jitter; Pk-Pk jitter; RMS jitter; SMIC standard CMOS process; frequency 100 MHz to 500 MHz; loop gain; low jitter ADPLL; power supply noise frequency; power supply noise rejection; size 0.13 mum; timing jitter estimation; Application specific integrated circuits; Clocks; Digital control; Integrated circuit noise; Jitter; Low-frequency noise; Microprocessors; Phase frequency detector; Power supplies; Working environment noise; ADPLL; Jitter; Power supply noise; Ring Oscillator;

fLanguage

English

Publisher

ieee

Conference_Titel

Industrial Technology (ICIT), 2010 IEEE International Conference on

Conference_Location

Vi a del Mar

Print_ISBN

978-1-4244-5695-6

Electronic_ISBN

978-1-4244-5696-3

Type

conf

DOI

10.1109/ICIT.2010.5472564

Filename

5472564