Building a common ESL design and verification methodology - is it just a dream?

In recent years, industry cooperation has established common language and methodology standards to support electronic system level (ESL) modeling, design and verification: SystemC, SystemC verification (SCV) and SystemC transaction level modeling (TLM). What is still conspicuously absent, is a common, standard methodology for ESL design and verification itself. As a result, leading ESL adopters have been forced to devise their own custom methodologies. Does everyone need to develop their own custom ´vertical´ methodology using standard ´horizontal´ languages, libraries, and data formats, or is it possible to devise a common, standard methodology - open to all - that would help to mainstream ESL design and verification? This panel of ESL users and suppliers will take a close look at what is being done today and debate the issues around what more is needed to address increasing system complexity. What are the major attributes and requirements for a standard methodology? How would it deliver the diverse requirements of algorithm development, system architecture exploration and optimization, integration and re-use of intellectual property (IP) from diverse sources, processor and coprocessor development, software development, RTL design, and testbench generation for system-to-implementation verification?