Variation-aware analysis: savior of the nanometer era?

VLSI engineers have traditionally used a variety of CAD analysis tools (e.g. SPICE) to deal with variability. As we go into deep sub micron issues, the analysis is becoming harder due to many secondary effects becoming primary. Panelists will debate the variability trend and present the order of importance of many variability trends (Vdd, Vt, interconnect, Leff, gate width) and their impact on design tools and methodologies. What new design tools, new modeling methodologies, and new (or old) design styles will combine to address variability? Will conservative design to accommodate variability halt the progress of Moore´s law? Is life as we know it over, or are we facing an opportunity for innovation in tools and design that will move us forward over the barriers that technology has placed in our path?