CMOS smart photosensor array for optoelectronic hit/miss transform processing of cervical smears

A CMOS smart photosensor test chip has been fabricated with a 24 × 24 smart photosensor array (SPA) to perform parallel postprocessing at the output plane of an optical correlator. The optical correlator comprises the first stage in a two-stage optoelectronic processor used to detect cancerous cells on cervical smear slides. The first stage of the processor uses the optoelectronic hit/miss transform (HMT) algorithm to rapidly scan the 2.5 GB of image data per slide for suspicious images. The output of this first stage consists of two time-sequential images coming from the optical correlator at rates up to 740 frames per second. To complete the first stage of processing a fast framing CCD camera must acquire the two images at a spatial resolution of 128×128 with 8 bits of grey scale per pixel. This produces an IO load of 97 Mbps which a digital framegrabber acquires in the controlling PC. The computer must then postprocess these two grey scale images in software or programmed DSP chips to complete the EIMT algorithm. The postprocessing consists of thresholding the two outputs of the correlator and then logically ANDing them to generate the finished HMT result, a binary image. The time required to serialize and process the correlator outputs in this fashion produces a IO bottleneck at the output of the first stage of the system. In contrast, a SPA at the same resolution and frame rate can reduce output bandwidth to 6 Mbps, 16 times less than the conventional CCD/DSP approach. In addition to reducing IO bandwidth, the SPA outputs the finished HMT result images thereby eliminating Image processing within the computer further freeing CPU time for other system control tasks