Synthesis of synchronous elastic architectures

Author

Cortadella, Jordi ; Kishinevsky, Mike ; Grundmann, Bill

Author_Institution

Univ. Politecnica de Catalunya, Barcelona

fYear

0

fDate

0-0 0

Firstpage

657

Lastpage

662

Abstract

A simple protocol for latency-insensitive design is presented. The main features of the protocol are the efficient implementation of elastic communication channels and the automatable design methodology. With this approach, fine-granularity elasticity can be introduced at the level of functional units (e.g. ALUs, memories). A formal specification of the protocol is defined and an efficient scheme for the implementation of elasticity that involves no datapath overhead is presented. The opportunities this protocol opens for microarchitectural design are discussed

Keywords

computer architecture; formal specification; network synthesis; protocols; system buses; automatable design methodology; elastic communication channels; latency-insensitive design; latency-tolerance; microarchitectural design; protocol formal specification; synchronous elastic architecture; Communication channels; Communication system control; Control systems; Delay; Design automation; Elasticity; Microarchitecture; Permission; Pipelines; Protocols; Design; Latency-insensitive design; Theory; Verification; latency-tolerance; protocols; synthesis;

fLanguage

English

Publisher

ieee

Conference_Titel

Design Automation Conference, 2006 43rd ACM/IEEE

Conference_Location

San Francisco, CA

ISSN

0738-100X

Print_ISBN

1-59593-381-6

Type

conf

DOI

10.1109/DAC.2006.229277

Filename

1688878