DocumentCode
2471205
Title
Mining global constraints for improving bounded sequential equivalence checking
Author
Wu, Weixin ; Hsiao, Michael S.
Author_Institution
Dept. of Electr. & Comput. Eng., Virginia Tech., Blacksburg, VA
fYear
0
fDate
0-0 0
Firstpage
743
Lastpage
748
Abstract
In this paper, we propose a novel technique on mining relationships in a sequential circuit to discover global constraints. In contrast to the traditional learning methods, our mining algorithm can find important relationships among several nodes efficiently. The nodes involved may often span several time-frames, thus improving the deducibility of the problem instance. Experimental results demonstrate that the application of these global constraints to SAT-based bounded sequential equivalence checking can achieve one to two orders of magnitude speedup. In addition, because it is orthogonal to the underlying SAT solver, it can help to enhance the efficacy of typical SAT based verification flows
Keywords
data mining; formal verification; logic testing; sequential circuits; SAT; global constraints; learning methods; mining algorithm; sequential circuit; sequential equivalence checking; verification; Algebra; Automatic test pattern generation; Circuit faults; Circuit simulation; Computational modeling; Costs; Learning systems; Logic circuits; Sequential circuits; Signal processing; Algorithms; Mining; Multi-node Constraint; SAT; Verification;
fLanguage
English
Publisher
ieee
Conference_Titel
Design Automation Conference, 2006 43rd ACM/IEEE
Conference_Location
San Francisco, CA
ISSN
0738-100X
Print_ISBN
1-59593-381-6
Type
conf
DOI
10.1109/DAC.2006.229319
Filename
1688895
Link To Document