DocumentCode :
2471320
Title :
Power factor correction using an enhancement-mode SiC JFET
Author :
Kelley, R.L. ; Mazzola, M. ; Morrison, S. ; Draper, W. ; Sankin, I. ; Sheridan, D. ; Casady, J.
Author_Institution :
SemiSouth Labs. Inc., Starkville, MS
fYear :
2008
fDate :
15-19 June 2008
Firstpage :
4766
Lastpage :
4769
Abstract :
The conventional wisdom that the SiC JFET is a normally on device has recently been superseded by the first practical normally off SiC JFET. The new true enhancement mode, three-terminal, pure-SiC design provides designers with a normally off solution that retains all the benefits of the normally on SiC JFET. With a simple change in the series gate impedance, the EM SiC JFET can be used with common IC drivers and is a drop-in replacement for current power devices in most applications. Device characteristics are superior to MOSFETs and IGBTs and offer the possibility of efficiency improvements from reduced conduction and switching losses. The work presented in this paper demonstrates the drop-in replacement of an IGBT with a normally off SiC JFET in a PFC demo circuit. System efficiency using each device was observed and compared. An improvement was noted with the JFET as expected.
Keywords :
JFET integrated circuits; driver circuits; integrated circuit design; power MOSFET; power factor correction; silicon compounds; wide band gap semiconductors; IC driver; MOSFET; SiC; enhancement-mode JFET; junction gate field effect transistor; power factor correction; series gate impedance; Insulated gate bipolar transistors; JFET circuits; MOSFETs; Power factor correction; Power transistors; Resistors; Schottky diodes; Semiconductor diodes; Silicon carbide; Voltage;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Power Electronics Specialists Conference, 2008. PESC 2008. IEEE
Conference_Location :
Rhodes
ISSN :
0275-9306
Print_ISBN :
978-1-4244-1667-7
Electronic_ISBN :
0275-9306
Type :
conf
DOI :
10.1109/PESC.2008.4592724
Filename :
4592724
Link To Document :
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