Title :
The importance of adopting a package-aware chip design flow
Author :
Sheth, Kaushik ; Sarto, Egino ; McGrath, Joel
Author_Institution :
Rio Design Autom., Santa Clara, CA
Abstract :
In this paper, we discuss about the short- and long-term implications of ignoring the relationship between the chip, package and PCB during I/O planning and how these issues manifest themselves as we move toward 65 and 45nm technology. It also introduces a whole new approach to chip/package I/O planning and optimization. This new approach simultaneously synthesizes the entire interconnect from the I/O driver to the package ball and establishes an interconnect plan that is optimized for both chip and package
Keywords :
integrated circuit design; integrated circuit interconnections; integrated circuit packaging; nanotechnology; I/O planning; interconnect plan; interconnect synthesis; package-aware chip design; Algorithm design and analysis; Chip scale packaging; Constraint optimization; Costs; Design automation; Design methodology; Design optimization; Integrated circuit interconnections; Integrated circuit packaging; Routing; Algorithms; Chip; Co-Design; Concurrent; Design; Experimentation; Exploration; Flip Chip; I/O; Package; Prototyping; RDL; Routing; Standardization; Substrate; Synthesis; Verification;
Conference_Titel :
Design Automation Conference, 2006 43rd ACM/IEEE
Conference_Location :
San Francisco, CA
Print_ISBN :
1-59593-381-6
DOI :
10.1109/DAC.2006.229240
