DocumentCode
2472025
Title
A local clocking approach for self-timed datapath designs
Author
Kim, Seokjin ; Sridhar, Ramalingam
Author_Institution
Dept. of Electr. & Comput. Eng., State Univ. of New York, Buffalo, NY, USA
fYear
1995
fDate
16-18 Mar 1995
Firstpage
152
Lastpage
155
Abstract
This paper presents the design and analysis of a local clock control circuit for the use of synchronous datapaths in an asynchronous environment. The design and the detailed simulation results of the circuit are given. A locally-clocked multiplier is designed and compared with several asynchronous implementations. The circuit provides an efficient method of asynchronous system implementation using synchronous datapaths
Keywords
asynchronous circuits; digital arithmetic; logic design; multiplying circuits; timing; asynchronous environment; asynchronous system implementation; local clock control circuit; locally-clocked multiplier; logic design; self-timed datapath designs; synchronous datapaths; CMOS logic circuits; Circuit faults; Clocks; Communication system control; Design methodology; Encoding; Mobile communication; Silicon; Timing; Very large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI, 1995. Proceedings., Fifth Great Lakes Symposium on
Conference_Location
Buffalo, NY
ISSN
1066-1395
Print_ISBN
0-8186-7035-5
Type
conf
DOI
10.1109/GLSV.1995.516043
Filename
516043
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