Title :
A novel procedure to evaluate design scalability based on device performance linked to photolithography data
Author :
Karklin, L. ; Balasinski, A. ; Axelrad, V.
Author_Institution :
Numerical Technol. Inc., San Jose, CA, USA
Abstract :
We propose a novel procedure to evaluate design manufacturability based on simulated photoresist patterns followed by extraction of MOSFET geometry and VT distribution. We demonstrate the procedure on a SRAM cell, to optimize photolithography for technology shrink from 0.16 to 0.13 /spl mu/m.
Keywords :
MOSFET; SRAM chips; integrated circuit design; integrated circuit manufacture; photolithography; photoresists; 0.16 to 0.13 mum; MOSFET geometry; SRAM cell; VT distribution; design manufacturability; design scalability; device performance; photolithography data; simulated photoresist patterns; technology shrink; FETs; Geometry; Image converters; Lenses; Lighting; Lithography; MOSFET circuits; Random access memory; Scalability; Silicon;
Conference_Titel :
Microprocesses and Nanotechnology Conference, 2000 International
Conference_Location :
Tokyo, Japan
Print_ISBN :
4-89114-004-6
DOI :
10.1109/IMNC.2000.872599
