Error vector magnitude of OFDM signals caused by sampling clock jitter

In the next-generation mobile communication system where the signal bandwidth is very broad, the sampling frequency of a digital-to-analog converter (DAC) and an analog-to-digital converter (ADC) in a transceiver becomes high. So the signal quality is sensitive to the jitter of the sampling clock. The relation between the error vector magnitude and the jitter of the sampling clock of a DAC generating baseband OFDM signal is simulated. The relation is also theoretically analyzed in the case when OFDM uses all the subcarriers of which the number equals FFT points. The theory agrees with the simulation results.