• DocumentCode
    2472537
  • Title

    Test response compactor with programmable selector

  • Author

    Mrugalski, Grzegorz ; Rajski, Janusz ; Tyszer, Jerzy

  • Author_Institution
    Mentor Graphics Corp., Wilsonville, OR
  • fYear
    0
  • fDate
    0-0 0
  • Firstpage
    1089
  • Lastpage
    1094
  • Abstract
    The paper presents an efficient method for synthesis of scan chain selection logic. It is capable of acting as a flexible X-control logic for test response compactors. The same circuitry can also be employed to selectively gate scan chains for diagnostic purposes
  • Keywords
    boundary scan testing; logic circuits; logic testing; VLSI test; X-control logic; gate scan chains; programmable selector; scan chain selection; test response compactor; Algorithm design and analysis; Built-in self-test; Circuit synthesis; Circuit testing; Clustering algorithms; Compaction; Feedback; Graphics; Logic testing; Reliability theory; Algorithms; Compression; Design; Reliability; Theory; VLSI test; scan chain selection; unknown states;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Design Automation Conference, 2006 43rd ACM/IEEE
  • Conference_Location
    San Francisco, CA
  • ISSN
    0738-100X
  • Print_ISBN
    1-59593-381-6
  • Type

    conf

  • DOI
    10.1109/DAC.2006.229402
  • Filename
    1688962
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2472537