Efficient sub-pixel interpolation and low power VLSI architecture for fractional motion estimation in H.264/AVC

In this paper we propose an efficient, low power algorithm and its co-designed VLSI architecture for fractional-pel motion estimation (FME) in H.264/AVC. Our fractional-pel motion estimator uses a simplified FIR filter for half-pel interpolation. Usage of this filter reduces the required number of computations and the memory size and bandwidth for half-pel interpolation. Our simulations compare our algorithm with the state-of-the-art, in terms of rate-distortion performance and computational complexity. Our VLSI architecture is prototyped on a Field Programmable System on Chip (FPSoC), comprising a Virtex-II Pro FPGA and an embedded PowerPC processor. Our results show that our algorithm on average has better rate-distortion performance, compared to previous state-of-the-art FME algorithms, while its losses compared to FME in H.264/AVC, are insignificant. Our prototyped architecture is more hardware-efficient than previous FPGA-based architectures, in terms of power consumption, throughput, area and memory utilization. We also show that its performance in terms of transistor count, throughput and power consumption, are comparable to that of state-of-the-art ASIC implementations.