Robust Design of CNFET Based Buffered Delay Model and Microwave Pulse Generator

This paper proposes an efficient and robust design of a CNFET based buffered delay circuit. The proposed circuit overcomes several issues of the traditional delay insertion circuits such as low- resolution, device-mismatch and so on. This work also designs a microwave pulse generator circuit using the proposed buffered delay circuit. Microwave pulses of pulse width 9.7 ps can be produced by the pulse generator presented in this paper. Further, variability of delay produced by proposed circuit has been analyzed to prove the immunity against process, voltage and temperature variations. CNFET based circuit proves to be more efficient as compared to its CMOS counterpart in terms of delay variability. The proposed buffered delay circuit also minimizes the effect of rise and fall time of the input signal. The proposed design of buffered delay circuit has been modeled using predictive technology model (PTM) @ 16-nm technology node and verified by simulation results on SPICE.