Simulation of Quantum Dot Flash Gate Stack with Lower Tunneling Voltages

Tunneling voltage of a nano-scale flash memory cell needs to be lowered considerably. This can be done only by employing very thin tunnel dielectrics. Quantum dot floating gate devices have shown a potential to do so in sub-65 nm regime. In this work, conventional and quantum dots´ FGMOS gate stacks for 65 nm and 45 nm technology nodes are simulated in Synopsys TCAD. The experiments are simulated for metal control gate structures with ultra-thin oxides with 3.3 nm and 2.5 nm thicknesses. Quantum dots arrangement is optimized to give similar results as that of a conventional structure. The devices exhibit significant memory windows with tunneling voltages as small as 12 V and 6 V, respectively, with quantum dot devices further requiring lesser tunneling times.