DocumentCode
2473409
Title
A 90 to 170V scalable P-LDMOS with accompanied high voltage PJFET
Author
Ellis-Monaghan, John ; Shi, Yun ; Sharma, Santosh ; Feilchenfeld, Natalie ; Letavic, Ted ; Phelps, Rick ; Hedges, Crystal ; Cook, Don ; Dunn, Jim
Author_Institution
Microelectron. Div., IBM, Essex Junction, VA, USA
fYear
2012
fDate
3-7 June 2012
Firstpage
129
Lastpage
132
Abstract
A novel JFET redesign of a laterally scaled P-LDMOS device is presented. The P-LDMOS device has excellent Rsp as it is scaled from 90V to 170V operation. This P-LDMOS design is modified to produce a 100V PJFET with good turn-off characteristics and a relatively low Vpinch of 3-7V.
Keywords
MIS devices; design; junction gate field effect transistors; P-LDMOS; design; high voltage PJFET; voltage 100 V; voltage 3 V to 7 V; voltage 90 V to 170 V; Breakdown voltage; Electric breakdown; Electric potential; Impact ionization; JFETs; Junctions; Logic gates; LDMOS; PJFET; PLDMOS; Power MOSFET; RESURF;
fLanguage
English
Publisher
ieee
Conference_Titel
Power Semiconductor Devices and ICs (ISPSD), 2012 24th International Symposium on
Conference_Location
Bruges
ISSN
1943-653X
Print_ISBN
978-1-4577-1594-5
Electronic_ISBN
1943-653X
Type
conf
DOI
10.1109/ISPSD.2012.6229040
Filename
6229040
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