• DocumentCode
    2473456
  • Title

    Statistical estimation of delay fault detectabilities and fault grading

  • Author

    Zhang, Zaifu ; McLeod, Robert D. ; Bridges, Greg E.

  • Author_Institution
    Dept. of Electr. & Comput. Eng., Manitoba Univ., Winnipeg, Man., Canada
  • fYear
    1995
  • fDate
    16-18 Mar 1995
  • Firstpage
    184
  • Lastpage
    187
  • Abstract
    In this paper, we present a statistical delay fault estimation technique. The basic method is an extension of STAFAN to include delay faults. A strategy to calculate the transition observabilities of fanout stems is proposed. Correlation within each fanout free region is considered in calculating gate line transition controllabilities. Results show this is a practical method of calculating detectabilities of delay faults. When compared with transition delay fault simulations, the estimations of fault coverage are within 2.3% for the benchmark circuits. Finally, the estimation technique is used to grade delay faults, with comparison to fault simulation results used to validate the method
  • Keywords
    VLSI; fault diagnosis; logic testing; statistical analysis; STAFAN; benchmark circuits; delay fault detectabilities; fanout free region; fanout stems; fault coverage; fault grading; gate line transition controllabilities; logic testing; statistical estimation; transition observabilities; Circuit faults; Circuit simulation; Circuit testing; Delay estimation; Electrical fault detection; Fault detection; Logic circuits; Logic testing; Pattern analysis; System testing;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    VLSI, 1995. Proceedings., Fifth Great Lakes Symposium on
  • Conference_Location
    Buffalo, NY
  • ISSN
    1066-1395
  • Print_ISBN
    0-8186-7035-5
  • Type

    conf

  • DOI
    10.1109/GLSV.1995.516049
  • Filename
    516049