A novel double-well isolation structure for high voltage ICs

Author

Sun, Weifeng ; Zhu, Jing ; Qian, Qinsong ; Hou, Bo ; Su, Wei ; Zhang, Sen

Author_Institution

Nat. ASIC Syst. Eng. Res. Center, Southeast Univ., Nanjing, China

fYear

2012

fDate

3-7 June 2012

Firstpage

193

Lastpage

196

Abstract

A novel double-well (DW) divided RESURF isolation structure featuring two slender N-Well regions at N^--Well, aiming at improving the off-state breakdown voltage for high voltage IC (HVIC) is proposed in this paper. The N-Well regions in the presented structure efficiently prevent N^--Well which used for the drift region of the Lateral Double Diffused MOSFET (LDMOS) from depleting with P-Well, so as to maintain the RESURF condition. The experiment results show that the proposed structure exhibits the breakdown voltage of 760V which has an improvement of 15% compared with the conventional structure.

Keywords

isolation technology; power MOSFET; power integrated circuits; semiconductor device breakdown; semiconductor device models; HVIC; LDMOS; P-Well; RESURF isolation structure; double-well isolation structure; high voltage IC; lateral double diffused MOSFET; off-state breakdown voltage; slender N-Well region; voltage 760 V; Breakdown voltage; Current measurement; Electric breakdown; Integrated circuits; Leakage current; Voltage control; Voltage measurement; divided RESURF; double well; high voltage ICs; isolation;

fLanguage

English

Publisher

ieee

Conference_Titel

Power Semiconductor Devices and ICs (ISPSD), 2012 24th International Symposium on

Conference_Location

Bruges

ISSN

1943-653X

Print_ISBN

978-1-4577-1594-5

Electronic_ISBN

1943-653X

Type

conf

DOI

10.1109/ISPSD.2012.6229056

Filename

6229056