Title :
Next generation I/O power delivery design through SIPD co-analysis & comprehensive platform validation
Author :
Tau, Yee Hung See ; Chan, Marcus
Author_Institution :
Intel Microelectron. (M) Sdn. Bhd., Penang Design Center (PDC), Penang, Malaysia
Abstract :
This paper illustrates different approaches in solving I/O power delivery noise issues and walk through pre-silicon design solution. It covers circuit and architectural design influence, on silicon and on board decoupling solutions selection and package and platform design optimization. SIPD co-simulations and appropriate package return path are the main topics to discuss and certainly impedance (Z) profile and transient analysis will be performed to observe the noise frequency and accurately address the root cause. All the above will be verified through comprehensive validation data.
Keywords :
power integrated circuits; I/O power delivery design; I/O power delivery noise; SIPD co-analysis; comprehensive platform validation; impedance profile; noise frequency; on board decoupling solutions; optimization; package return path; pre-silicon design solution; transient analysis; Capacitors; Circuit noise; Design optimization; Impedance; Inductance; Packaging; Power system modeling; Silicon; Variable structure systems; Working environment noise;
Conference_Titel :
Electrical Performance of Electronic Packaging and Systems, 2009. EPEPS '09. IEEE 18th Conference on
Conference_Location :
Portland, OR
Print_ISBN :
978-1-4244-4447-2
Electronic_ISBN :
978-1-4244-5646-8
DOI :
10.1109/EPEPS.2009.5338441
