Low specific on-resistance p-type OPTVLDLDMOS with double hole-conductive paths for SPIC application

Author

Cheng, Junji ; Chen, Xingbi

Author_Institution

State Key Lab. of Electron. Thin Films & Integrated Devices of China, Univ. of Electron. Sci. & Technol., Chengdu, China

fYear

2012

fDate

3-7 June 2012

Firstpage

225

Lastpage

228

Abstract

A novel p-type DP-OPTVLD (Double-Paths & OPTimum-Variational-Lateral-Doping) LDMOS is proposed. It features the double hole-conductive paths formed by a top and a buried p-layer in the drift region using OPTVLD technique, which significantly contribute to reducing device specific on-resistance. The design principle and electrical characteristics of the proposed structure are investigated theoretically and experimentally. Simulation results show that the specific on-resistances are 155/689 mΩ·cm² with breakdown voltages of 300/800 V for the proposed structure, respectively, which are less than 60% of that with corresponding breakdown voltages for the conventional structure. This structure used as high-side can apply to SPIC with a low integration difficulty and a low fabrication cost.

Keywords

MIS devices; MOS integrated circuits; electric breakdown; OPTVLD technique; SPIC application; double hole-conductive paths; double-paths; drift region; electrical characteristics; fabrication cost; low specific on-resistance p-type OPTVLDLDMOS; optimum-variational-lateral-doping; voltage 300 V; voltage 800 V; Approximation methods; Breakdown voltage; Doping; Electric fields; Junctions; Performance evaluation; Simulation; OPTVLD; SPIC; double-paths; high-side;

fLanguage

English

Publisher

ieee

Conference_Titel

Power Semiconductor Devices and ICs (ISPSD), 2012 24th International Symposium on

Conference_Location

Bruges

ISSN

1943-653X

Print_ISBN

978-1-4577-1594-5

Electronic_ISBN

1943-653X

Type

conf

DOI

10.1109/ISPSD.2012.6229064

Filename

6229064