Improved FPGA implementation of Probabilistic Neural Network for neural decoding

Probabilistic Neural Network has been considered as providing superior performance for neural decoding. However, the huge computation burden costs high resource in FPGA, which limits its scalability. In this paper, an improved FPGA implementation of Probabilistic Neural Network for neural decoding is developed and evaluated on the Xilinx Virtex-5 platform. The proposed implementation reduces the resource utilization, and enhances the scalability of the FPGA implementation of the Probabilistic Neural Network greatly.