DocumentCode
2474229
Title
Fast algorithm for performance-oriented Steiner routing
Author
Borah, Manjit ; Owens, Robert Michael ; Irwin, Mary Jane
Author_Institution
Dept. of Comput. Sci. & Eng., Pennsylvania State Univ., University Park, PA, USA
fYear
1995
fDate
16-18 Mar 1995
Firstpage
198
Lastpage
203
Abstract
We present a routing algorithm which minimizes the Elmore delay to the identified critical sinks while producing routes comparable to the best previously existing Steiner router. Since performance oriented layout generators employ iterative techniques that require a large number of calls to the routing algorithm for layout evaluation, a fast algorithm for routing is desirable. Our algorithm has a fast (O(n2 ), where n is the number of points) and practical implementation using simple data structures and techniques. Comparisons with other existing algorithms are presented along with results from a performance driven layout generator using our routing algorithm
Keywords
VLSI; circuit layout CAD; computational complexity; data structures; delays; integrated circuit layout; iterative methods; network routing; Elmore delay minimisation; data structures; fast routing algorithm; iterative techniques; layout generators; performance-oriented Steiner routing; Circuits; Computer science; Data structures; Delay; Iterative algorithms; Routing; Space exploration; Timing; Very large scale integration; Wire;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI, 1995. Proceedings., Fifth Great Lakes Symposium on
Conference_Location
Buffalo, NY
ISSN
1066-1395
Print_ISBN
0-8186-7035-5
Type
conf
DOI
10.1109/GLSV.1995.516052
Filename
516052
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