A two-level optimization scheme for bandwidth optimization of a microprocessor vertical interconnect

A parametric model of a generic differential ten-layer microprocessor package line with two motherboard layers has been developed. A dimensionality reduction scheme and a reusable, multi-dimensional look-up table precede the global optimization phase which is facilitated by a smooth interpolation scheme based on splines. An accelerated boundary element based full-wave electromagnetic solver has been used to construct a look-up table of S-parameters for a number of designs. The second phase features a custom local optimizer incorporating all the variables without any dimension reduction. This methodology has been applied to automated synthesis of the differential package line resulting in a significant improvement of the return loss performance.