• DocumentCode
    2474327
  • Title

    Imprint lithography using triple-layer-resist and its application to MOSFET fabrication

  • Author

    Nakamura, H. ; Baba, A. ; Asano, T.

  • Author_Institution
    Center for Microelectron. Syst., Kyushu Inst. of Technol., Fukuoka, Japan
  • fYear
    2000
  • fDate
    11-13 July 2000
  • Firstpage
    232
  • Lastpage
    233
  • Abstract
    In this paper, we report pattern transfer characteristic of the imprint lithography by employing a triple-layer-resist method. In addition, fabrication of MOSFETs having the gate length down to 100 nm is demonstrated. Gate oxide integrity is also tested in order to investigate mechanical damage of the imprint stress on devices.
  • Keywords
    MOSFET; lithography; resists; 100 nm; MOSFET fabrication; gate oxide integrity; imprint lithography; mechanical damage; pattern transfer; triple layer resist; Crystalline materials; Etching; Fabrication; Large scale integration; Lithography; MOSFET circuits; Microelectronics; Plasma temperature; Resists; Testing;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Microprocesses and Nanotechnology Conference, 2000 International
  • Conference_Location
    Tokyo, Japan
  • Print_ISBN
    4-89114-004-6
  • Type

    conf

  • DOI
    10.1109/IMNC.2000.872730
  • Filename
    872730
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2474327