Title :
Electrical modeling of annular and co-axial TSVs considering MOS capacitance effects
Author :
Bandyopadhyay, Tapobrata ; Chatterjee, Ritwik ; Chung, Daehyun ; Swaminathan, Madhavan ; Tummala, Rao
Author_Institution :
Microsyst. Packaging Res. Center, Georgia Inst. of Technol., Atlanta, GA, USA
Abstract :
This paper presents analytical modeling and parametric study of the voltage dependent metal-oxide-semiconductor (MOS) capacitance of annular and co-axial TSVs. 3D electromagnetic (EM) simulations of TSVs are performed considering the depletion region. A low loss TSV structure is proposed utilizing the MOS capacitance effect.
Keywords :
MOS integrated circuits; capacitance; integrated circuit modelling; 3D electromagnetic simulations; MOS capacitance effects; analytical modeling; annular TSV; co-axial TSV; depletion region; electrical modeling; through silicon vias; voltage dependent metal-oxide-semiconductor capacitance; Analytical models; Capacitance; Channel bank filters; Dielectric losses; Dielectric substrates; Packaging; Parametric study; Temperature; Through-silicon vias; Voltage;
Conference_Titel :
Electrical Performance of Electronic Packaging and Systems, 2009. EPEPS '09. IEEE 18th Conference on
Conference_Location :
Portland, OR
Print_ISBN :
978-1-4244-4447-2
Electronic_ISBN :
978-1-4244-5646-8
DOI :
10.1109/EPEPS.2009.5338462
