Title :
Verification of robustness of digital CMOS circuits
Author_Institution :
Dept. of Phys. & Measur. Technol., Linkoping Univ.
Abstract :
A method to verify that a digital CMOS design is insensitive to variations in process parameters has been developed. During simulation the parts of a design which turn out to be sensitive to variations in detail are pointed out to the designer. This also gives an indication of what parts can be redesigned more aggressively to achieve better performance. Intrachip deviation and interchip deviation are treated separately to avoid inadequate uncertainty
Keywords :
CMOS integrated circuits; digital integrated circuits; integrated circuit technology; sensitivity analysis; CMOS design; digital CMOS circuits; interchip deviation; intrachip deviation; robustness verification; sensitivity analysis; CMOS digital integrated circuits; Capacitance; Circuit simulation; Circuit testing; Delay; Discrete event simulation; Probability; Robustness; Switches; Timing;
Conference_Titel :
Circuits and Systems, 1988., IEEE International Symposium on
Conference_Location :
Espoo
DOI :
10.1109/ISCAS.1988.15361
