DocumentCode
2474632
Title
Application of surrogate modeling to generate compact and PVT-sensitive IBIS models
Author
Zhu, Ting ; Franzon, Paul D.
Author_Institution
ECE, NCSU, Raleigh, NC, USA
fYear
2009
fDate
19-21 Oct. 2009
Firstpage
77
Lastpage
80
Abstract
A new proposal of applying surrogate-modeling in input-output buffer information specification (IBIS) is presented. It saves the IBIS data storage resource, extends the model utility to various process-voltage-temperature (PVT) simulations and eliminates the data interpolation deviations.
Keywords
buffer circuits; buffer storage; circuit simulation; integrated circuit modelling; IBIS data storage resource; IBIS model; input-output buffer information specification; model utility; process-voltage-temperature simulation; surrogate modeling; Circuit simulation; Digital systems; Interpolation; Memory; Power system modeling; Proposals; Signal analysis; Table lookup; Timing; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Electrical Performance of Electronic Packaging and Systems, 2009. EPEPS '09. IEEE 18th Conference on
Conference_Location
Portland, OR
Print_ISBN
978-1-4244-4447-2
Electronic_ISBN
978-1-4244-5646-8
Type
conf
DOI
10.1109/EPEPS.2009.5338472
Filename
5338472
Link To Document