Clock jitter modeling in statistical link simulation

Statistical link analysis has gained significant importance as high-speed interconnect designs require accurate bit error rate prediction with device jitter and noise. Currently available statistical analysis techniques focus on modeling of data channels and the impact of a clock channel is often ignored or primitively approximated using a simple receiver sampling distribution. Thus, it ignores any jitter tracking between data and clock signals. In this paper, a general formulation is presented to model the common jitter source between data and clock signals in order to capture any jitter tracking between them. To demonstrate the usage of the proposed formulation, we have derived various models for commonly used clocking architectures, such as the forwarded clocking scheme in XDRtrade, DDR, and GDDR systems and the common source RefClk architecture used in PCIe channels. The formulation is verified numerically by using an internally developed CAD tool.