Low-power self-equalizing driver for silicon carrier interconnects with low bit error rate

Author

Gadfort, Peter ; Franzon, Paul D.

Author_Institution

Dept. of Electr. & Comput. Eng., North Carolina State Univ., Raleigh, NC, USA

fYear

2009

fDate

19-21 Oct. 2009

Firstpage

37

Lastpage

40

Abstract

This paper demonstrates and compares the power efficiency of a standard differential current mode driver operating over an FR-4 channel with an improved driver with pre-emphasis operating over a silicon carrier channel. The drivers were designed for a 45 nm process, and both achieved a bit error rate of 10^-15 errors per bit while operating at 4 Gbps. The power of the improved driver was reduced to one-fourth that of the standard driver through the utilization of the silicon carrier channels and pre-emphasis.

Keywords

current-mode circuits; driver circuits; elemental semiconductors; error statistics; integrated circuit design; integrated circuit interconnections; low-power electronics; silicon; FR-4 channel; Si; bit error rate; bit rate 4 Gbit/s; differential current mode driver design; low-power self-equalizing driver; power efficiency; silicon carrier interconnects; size 45 nm; Bit error rate; Copper; Cutoff frequency; Digital systems; Driver circuits; Integrated circuit interconnections; Packaging; Propagation delay; Radio frequency; Silicon;

fLanguage

English

Publisher

ieee

Conference_Titel

Electrical Performance of Electronic Packaging and Systems, 2009. EPEPS '09. IEEE 18th Conference on

Conference_Location

Portland, OR

Print_ISBN

978-1-4244-4447-2

Electronic_ISBN

978-1-4244-5646-8

Type

conf

DOI

10.1109/EPEPS.2009.5338482

Filename

5338482