Low pin count DfT technique for RFID ICs

The need of uniquely identifiable objects for multiple applications has given great attention to RFID ICs over the years. The test challenges imposed by the nature of this type of IC include small die size, reduced number of external pins, low power mixed-signal design and the need of a low cost production test. In this work, a DfT technique for RFID ICs that deals with some of these limitations is presented. The method requires only 3 external test pins. Results show that the proposed method allows combining and managing functional tests (used for testing most of the analog parts of the chip) and structural test (scan test) reaching high fault coverage. A test control unit and a test wrapper are added to the core. The architecture of the test control unit is presented as well as area, test coverage and test time results.