Design and characterization of a 12.8GB/s low power differential memory system for mobile applications

This paper describes the design and characterization of a low power differential memory interface targeted for mobile applications. The initial design of the memory interface achieves 2.7 to 4.3 GB/s data bandwidth and consumes 3.3 mW/Gb/s at 4.3 GB/s operation. The design allows two x16 stacked dies to be fit into a 12 mm PoP package, achieving a 12.8GB/s aggregated data bandwidth based on 3.2 Gb/s per pin. A low swing signaling based on a voltage-mode differential driver is reviewed and its performance is analyzed. We demonstrate that, compared to LPDDR2 memory interface based on single-ended signaling, the differential memory interface overcomes most of channel related issues such as crosstalk and SSO noise and provides a very clean channel response. Thus, the resulting extra system margin can be used to compensate for extra timing jitter and system noise, enabling lower power and lower system cost. To evaluate the impact of timing jitter and system noise to system performance, a statistical link modeling and simulation methodology is employed. Two test systems are built based on wirebond-based Package-on-Package (PoP) and BGA-based Chip-to-Chip (C2C) module to characterize the memory system performance and to validate the memory statistical link model. The correlation result showed a good agreement in the system bit error rates (BER) between measurement and simulation.