FPGA implementation of peak cancellation for PAPR reduction of OFDM signals

Peak-to-average power ratio (PAPR) reduction techniques play an important role for achieving highly efficient operation of power amplifiers. Peak cancellation (PC), known as a computationally efficient PAPR reduction method, has several advantages over other techniques. In this paper, a cost-effective implementation scheme for PC is presented. The design methodology and practical implementation issues based on field-programmable gate array (FPGA) are discussed, with particular emphasis on the resulting resource utilizations. The experimental results show that in certain scenarios, our approach outperforms the well-known clipping and filtering (CAF) approach in terms of achievable error vector magnitude (EVM) and adjacent channel leakage ratio (ACLR), with much lower hardware overhead.