Dual-edge-triggered FF with timing error detection capability

This paper presents a construction of dual-edge-triggered flip-flops (DET-FFs) with timing error detection capability. The proposed FF is based on a conventional DET-FF and a conventional timing error detection method. While the conventional timing error detection uses a transition detector with the area of large, the proposed FF uses internal signals in a DET-FF as an alternative of the transition detector. This paper also shows an evaluation result indicating that the proposed FF has ten percent or smaller area overhead and lower power consumption than the simple combination of the conventional DET-FF and timing error detection methods.