Dirty data vulnerability mitigation by means of sharing management in cache coherence protocols

In this paper, a comprehensive study is firstly conducted to determine the effects of cache coherence protocols on the characteristics of cache memories in current multi-core processors. The main focus of this study is to analyze the effects of coherence protocols on the susceptibility of last level caches. The outcomes of this analysis indicate that differences in handling dirty data items play an important role to make distinction in favor of or against a cache coherence protocol. Based on the results of first step, two efficient schemes are introduced to manage sharing of the dirty data items among different same-level caches. These schemes are built on an effective LRU-based prediction that helps to determine the cores which will access dirty cache blocks in the near future. The proposed schemes leads to about 13% improvement in vulnerability factor, with no performance degradation and with negligible bandwidth overhead compared to previous cache coherence protocols.