FPGA-based implementation of Synchronous Petri Nets

This paper describes a flexible and systematic implementation method of Petri Nets that can be applied to high speed parallel control. This paper suggests a hard-wired implementation for a high frequency clock-driven system with little jitter. To implement Petri Nets with synchronous (clock-driven) digital circuits, a Synchronous Petri Net is proposed. The suggested implementation method is based on a regular cell-array such as FPGA (field programmable gate array). Radix-k Petri Net and Radix-k conversion are defined to solve technology mapping problem of FPGA that consists of k-size cells. Cell usage, cell utilization, cell complexity, and speed index are defined and derived, which are used for quantitative analysis and efficient design. To help the design process, necessary CAD tools such as design entry library, hard-macro library, and net-list converter are developed. The suggested method is demonstrated using Xilinx FPGA, and its operation is verified by computer simulations