Performance analysis and simulation of the SOME-Bus architecture using message passing

The simultaneous optical multiprocessor exchange bus (SOME-Bus) is a low-latency, high-bandwidth, fiber-optic interconnection network which directly links arbitrary pairs of processor nodes without contention. It contains a dedicated channel (of b bits) for the data output of each node, eliminating the need for global arbitration and providing bandwidth that scales directly with the number of nodes in the system. Each of N nodes has an array of receivers, with one receiver dedicated to each node output channel. The entire N-receiver array can be integrated an a single chip at a comparatively minor cost resulting in O(N) complexity. The receiver number remains constant as b is increased. This paper examines the performance of the SOME-Bus using a message-passing queueing network model. It develops theoretical results which provide distributions of messages in the system and predict processor utilization and message waiting time. It also presents simulation results which validate the theoretical results and compare processor utilization in the SOME-Bus, the crossbar and the torus using queueing network models, with and without synchronization. It demonstrates that, compared to the networks considered here, the SOME-Bus is the interconnection network whose performance is least affected by large message communication times. Even in the presence of intense synchronization, processor utilization remains practically unaffected while it drops quite dramatically in the other architectures