AMS static voltage level check

This paper and presentation describes a methodology for checking multi voltage levels on multiple power domains for analog and mixed signal circuits. Traditional AMS verification does not account for electrical characteristics such as voltage levels in any connection between two discrete ports. Such flows only focus on the functionality aspect of the verification. That leaves a major hole in the verification process, the result of which can lead to a non-functional chip or future reliability problems with that chip. With proper AMS discipline planning, AMS designer block discipline resolution (BDR) can be applied to check for voltage mismatches statically (zero time simulation) at elaboration time. It is a very efficient and easy to add additional step to the functional verification approach. This step increases the coverage and serves as an important tool to help address voltage mismatch and reach silicon success first time round.