• DocumentCode
    2479529
  • Title

    The MPC5005 RISC microcontroller

  • Author

    Melear, Charles

  • Author_Institution
    Motorola Inc., Austin, TX, USA
  • fYear
    1995
  • fDate
    7-9 Mar 1995
  • Firstpage
    79
  • Lastpage
    83
  • Abstract
    The MPC505 microcontroller is the first implementation of a new family of microcontrollers that features a reduced instruction set (RISC) architecture based on the Power PC architecture. The internal architecture of the MPC505 implements a 32-bit structure. This architecture provides 32-bit effective addresses, integer data types of 8-, 16-, and 32-bits and floating point data types of 32 and 64 bits. A simplified block diagram of the MPC505 is shown in fig. 1. The MPC505 is designed to operate at 3.3 volts. Along with power conservation features, such as clock speed reduction, the MPC505 can operate on a relatively modest power budget
  • Keywords
    computer architecture; floating point arithmetic; microcontrollers; real-time systems; reduced instruction set computing; 3.3 V; 32 bit; Motorola MPC505 microcontroller; Power PC architecture; RISC microcontroller; effective addresses; floating point data types; integer data types; power budget; power conservation features; reduced instruction set; Microcontrollers; Random access memory; Reduced instruction set computing;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Southcon/95. Conference Record
  • Conference_Location
    Fort Lauderdale, FL
  • Print_ISBN
    0-7803-2576-1
  • Type

    conf

  • DOI
    10.1109/SOUTHC.1995.516081
  • Filename
    516081