Power gating multiplier of embedded processor datapath

Leakage power is an important concern in modern electronic designs. To efficiently employ power gating for leakage reduction in embedded processors, the architecture must provide a clear-cut software support for power gating and the power-gated unit must have significant idle times during the execution of the applications. We introduce power gating of individual datapath units for the embedded architecture of FlexCore, to evaluate if leakage reductions in temporarily idle units can reduce the overall power dissipation of compute-intensive applications. Post-layout multi-corner simulations for a 65-nm FlexCore datapath implementation demonstrate that power gating of the multiplier unit yields overall datapath energy savings, up to 14%, for two EEMBC benchmarks.